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The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 4.0, 1G to 400G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers signal integrity and jitter performance that exceeds the standards' electrical specifications.

The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Coding Sublayer (PCS) and Media Access Control (MAC) to reduce design time and to help designers achieve first-pass silicon success.


  • Supports 1.25 to 25.8 Gbps data-rate
  • Supports PCI Express 4.0 with lane margining, 1G to 400G Ethernet, CCIX, and SATA protocols
  • Supports x1 to x16 macro configurations with aggregation and bifurcation
  • Spread Spectrum Clock (SSC)
  • PCIe Separate Refclk Independent SSC (SRIS) and power management features
  • Ethernet Electrical Energy Efficient (EEE)
  • Reference clock sharing for aggregated macro configurations
  • Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • Supports IEEE 1149.6 AC Boundary Scan

Tech Specs

Market SegmentIndustrial and Military Civil Aerospace, Communications, Others, Automotive, Consumer Electronics, Data Processing
Maturity Available on request


  • Includes one, two or four full-duplex transceivers (transmit and receive functions)
  • Supports back channel initialization, aggregation, bifurcation, and power management
  • Supports both internal and external reference clock connections to the PHY
  • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
  • Contains embedded 7-, 9-, 11-, 15-, 16-, 23- and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
  • Fully controllable via the integrated logic core and the test access port (TAP)
  • Embedded BERT and internal eye monitor


  • Verilog models and test bench
  • Protocol-specific test bench
  • Liberty timing views (.lib)
  • LEF abstracts (.lef)
  • CDL netlist (.cdl)
  • IP-XACT XML files with register details
  • ATPG models
  • IBIS-AMI models
  • Documentation

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