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6G PHY in TSMC (16nm)

Overview

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) cost, low-power consumption in consumer applications. The multi-protocol 6G PHY IP provides low active and standby power while exceeding signal integrity and jitter performance of PCI Express 2.1, SATA 6G, SGMII, XAUI, and CEI-6G specifications. The PHY incorporates advanced power saving features such as PCI Express L1 sub-states power management and power gating in standby mode of operation.

The hybrid transmit drivers support low power voltage mode and high swing current mode for further active power savings. The PHY's Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.

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