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The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 16G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards' electrical specifications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards including PCI Express, SATA, Ethernet, OBSI/CPRI, JESD204, Serial Rapid I/O and other industry-standard interconnect protocols. The DesignWare Multi-Protocol 16G PHY IP is optimized to meet the needs of applications with high-speed port side, chip-to-chip, and backplane interfaces.

The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY supports low standby power with advanced L1 substates and low active power with I/O supply under drive, decision feedback equalization (DFE) bypass and V-Boost off. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerate time-to-market.


  • Supports 1.25 to 16 Gbps data-rates
  • Supports x1, x2, and x4 macro configurations
  • Supports PCI Express 4.0, SATA 6G, Ethernet
  • Supports x1 and x16 macro configuration with aggregation and bifurcation
  • Superior SI across lossy backplanes enabled by adaptive continuous time linear equalizer (CTLE), (DFE)
  • and feed forward equalization (FFE)
  • Spread Spectrum Clock (SSC) and separate Refclk Independent SSC (SRIS)
  • Reference clock sharing for aggregated macro configurations
  • Embedded bit error rate (BER) tester and internal eye monitor
  • IEEE 802.3az Electrical Energy Efficient (EEE)
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40°C to 125°C Tj

Tech Specs

Market SegmentIndustrial and Military Civil Aerospace, Communications, Others, Automotive, Consumer Electronics, Data Processing
Maturity Available on request


  • Optimized for low power and small area
  • Supports PCIe lane margining
  • Includes one, two or four full-duplex transceivers (transmit and receive functions)
  • Physical coding sublayer (PCS) blocks for PCIe, SATA, and Ethernet, supporting backchannel initialization,
  • aggregation, bifurcation, and power management
  • Multi-lane PHY shares a single clock and support core
  • Provides high-speed serial and low-speed parallel clocks to both the transceiver and PCS.
  • Supports both internal and external reference clock connections to the PHY
  • Configurable transmitter and receiver equalization
  • Supports chip-to-chip, port side and backplane interfaces
  • Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
  • Contains embedded 7-, 9-, 11-, 15-, 16-, 23- and 31-bit pseudo random bit sequencer (PRBS) for internal
  • and external loopbacks
  • Fully controllable via the integrated logic core and the test access port (TAP)
  • Embedded bit error rate (BER) tester and internal eye monitor


  • Verilog models and test bench
  • Protocol-specific test bench
  • Liberty timing views (.lib)
  • LEF abstracts (.lef)
  • CDL netlist (.cdl)
  • IP-XACT XML files with register details
  • ATPG models
  • IBIS-AMI models
  • Documentation

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