|
||
![]() www.design-reuse-embedded.com |
You are here : design-reuse-embedded.com
> Monitoring and Verification
> Simulation and Verification
TileLink VIP
|
|
Overview TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC. The SmartDV s TileLink Verification IP is fully compliant with standard TileLink Specification and provides the following features. TileLink VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Please sign in to view full IP description :
|
Partner with us |
List your ProductsSuppliers, list and add your products for free. |
More about D&R Privacy Policy© 2024 Design And Reuse All Rights Reserved. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. |
||||||