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VIP for DisplayPort 2.0

All Silicon IP All Verification IP

Overview

The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for DisplayPort 2.0 is compatible with all main verification languages such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera; and methodologies such as UVM, OVM, and VMM; and runs on all leading simulators.

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