www.design-reuse-embedded.com
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...
You are here : design-reuse-embedded.com  > Verification Platform  > Simulation and Verification
Online Datasheet        Request More Info
All Silicon IP All Verification IP

Overview

The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for DisplayPort 2.0 is compatible with all main verification languages such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera; and methodologies such as UVM, OVM, and VMM; and runs on all leading simulators.

Benefits

The Cadence VIP for DisplayPort 2.0 supports the following VESA specifications: 

  • DisplayPort versions 1.2a, 1.3, 1.4, 1.4a, and 2.0

  • Embedded DisplayPort (eDP) versions 1.3, 1.4a, 1.4b, and 1.5

The specifications are available at http://www.vesa.org.

Partner with us

Visit our new Partnership Portal for more information.

Submit your material

Submit hot news, product or article.

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2018 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted,
reposted, duplicated or otherwise used without the
express written permission of Design And Reuse.