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The Cadence® IP Solution for GDDR6 consists of PHY, controller, and Verification IP (VIP) serving very-high-bandwidth memory applications. With PHY availability in 7nm semiconductor process technology, the solution is ideal for applications including machine learning, AI, cryptocurrency mining, graphics, automated driving, ADAS, and high-performance computing (HPC).


  • Leverages design technology from Cadence's silicon-proven DDR and high-speed SerDes designs, resulting in lower risk when implementing GDDR6
  • Low BER reduces retries on the memory bus, providing greater bandwidth and lower maximum latency
  • Wide design margin allows users to implement GDDR6 on PCBs with common materials such as FR4, reducing the cost of GDDR6 deployment
  • Available GDDR6 reference design allows users to replicate Cadence's test-chip results in their own products
  • Industry-leading VIP, now extended with GDDR6 support, enables robust verification of the GDDR6 interface in context of the full SoC


With other solutions, system bring-up is gated by the need for customers to write their own firmware U-Boot code in order for the SoC's CPU to boot DRAM. This can result in the long-awaited first silicon sitting in the lab for days or weeks–after all, nothing works until the DRAM works.

However, with the Cadence GDDR6 IP bring-up approach, users can:

  • Directly access DRAM controller and PHY registers through JTAG
  • Bring up DRAM interface fast–typically in one day
  • Use software that allows 2D eye shmoo on any pin–without probing
  • Easily port DRAM parameters into chip-level firmware
  • Allow Cadence staff to remotely and securely debug DRAM interface issues

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