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The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint. The family of IPX-AES IP-Cores is an encryptor / decryptor core range that efficiently implements in FPGA the Advanced Encryption Standard as specified in the Federal Information Processing publication FIPS-197 of the National Institute of Standards and Technology. The IPX-AES module can be customized to ensure its optimization for a wide range of specific application fields with a design architecture that can be adapted to support from low up to very high bit-rates. Its flexibility allows combining several functions and operating modes on very small footprints.


Multiple stream management Renewable security FIPS compliant


Digital Cinema (DCI), Secure Content applications in Broadcast, Post-production, Archiving, Video Surveillance, Medical Imaging. Digital Right Management (DRM)

Block Diagram


Functions With addressing keys of 128, the IPX-AES cores execute decryption or encryption. Data-stream handling The IPX-AES cores can handle the data and secret keys in two different ways. The single stream option consists of a core capable of managing data with a single key, before a new update of this key. The multiple stream option is a feature capable of managing multiple ciphering processes together, each based on a different secret key. Chaining modes The inter-data-block chaining supports all existing modes that can be used separately or combined into a single design: ECB (Electronic Code-Book), CBC (Cipher Block Chaining), CTR (Counter). Other modes could be supported. Data busses The incoming, outgoing and key data are handled on either common or separate buses. Data bus width is 128 bits wide. Clock The processes use a single clock and can be reset asynchronously.

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