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All Silicon IP

Overview

INT 25011 is the only SOC IP Core that implements a full 25G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation. It provides the lowest latency and highest performance in the industry.

INT 25011 has built in advanced architectural flexibility that provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others and customize them for their specific design application.

INT 25011 can process TCP/IP sessions as client/server in mixed session mode for Network equipment and in-line network security appliances, simultaneously, at 25-G-bit rate. This relieves the host CPU from costly TCP/IP software related session setup/tear down, data copying and maintenance tasks thereby delivering 10x to 20x TCP/IP network performance improvement when compared with TCP/IP software.

INT 25011 also implements IGMP V1/V1/V3 protocol processing in hardware across all sessions. Available as an option to save BRAM and logic resources.

Benefits

  • Featuring APIs at different levels the General TOE allows the application developer to easily migrate from software, to TOE hardware, to custom hardware, to achieve higher performance.
  • ~ 74G bit full duplex Throughput
  • Very low application to application latency

Applications

High performance Cloud Servers, security appliances, Web Servers, Application servers, NICs, SAN/NAS and data center equipment design applications

Block Diagram

Features

  • Highly customizable hardware IP block
  • Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow
  • All stages of Full TCP stack implemented in High performance hardware
  • Ultra-Low Latency through 25 G TOE around 130+ ns
  • Native 25G Architecture running at full 25G Network line rate
  • Ultra-High Throughput: Receives and Sends sustained large TCP payloads, depending upon remote server/client’s capability.
  • Fully Integrated and tested on Altera/Xilinx FPGAs; TOE+Host_I/F SoC IP bundle

Deliverables

  • NetList. All TCP and or UDP configuration files, FPGA libs and many more
  • Test Bench, ,vcd files, configuration code/API models for various components e.g. TCP/IP Client and Server models, transaction model (optional)
  • External memory interface/model (optional)
  • TCP Model (optional)
  • Verification suite (optional)
  • Test packet-traffic suite (optional)

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