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16 "Simulation and Verification" Solutions

1
Cadence Verification Suite
Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

2
Perspec System Verifier
Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days.

3
VIP for DisplayPort 2.0
The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K.

4
Xcelium Simulation on Arm-Based Servers
Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC).

5
SD Express Card Verification IP
Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

6
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

7
NVMe-Xactor VIP Solution
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

8
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

9
SimAccel FPGA-Accelerated Verification
Accelerate RTL Verification and SW Bring-up Target IPs and SoCs
  • NVMe controller
  • PCIe RC/EP IP, Repeater, Switch
  • Flash controller
  • AMBA NoCs and peripherals
  • M...

10
SimCluster GLS
Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

11
SimXACT - Gate Simulation Productivity and Analysis Technology
Gate-Level X-Verification : Reduce Bring-up Time

12
TileLink VIP
TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC.

13
Multi-domain simulation at the system-level for mixed signal behavior modeling
VisualSim Simulation Technology - heterogeneous models of computation

14
Performance modeling using stochastic components
In VisualSim Architect, one can model designs as stochastic processes, with library blocks and simulators supporting the same. The latency, in seconds, and throughput, measured in Mbps, gives the efficiency of the stochastic process. Designer can put into use, different use cases and get the expected output.

15
Display Emulation/Testing Platform
SiWave develops innovative solutions for the embedded market. We have been in business since 2003 and have successfully delivered a number of projects targeting different industry standards. We sell o...

16
RISC-V formal verification

Modern processors implement numerous optimizations for power, performance, and area. Optimizations such as pipelining, interlocking, and data forwarding introduce numerous data dependencies and haz...


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