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   Alma Technologies is a semiconductor IP provider, designing high-quality FPGA and ASIC IP Cores since 2001. Its products stand out for their engineering, being complete, easy-to-use and reliable IP solutions. World-class technical support and a long track record of proven designs by more than 200 licensees in over 20 countries provide Alma Technologies customers with excellent service and great value. Available either as standalone, high quality and implementation technology independent VHDL or Verilog RTL, or as optimized Netlists for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices, Alma Technologies IPs are designed to ensure a fast and trouble-free integration in any FPGA or ASIC design.   
10 SoCs

1
Scalable Ultra-High Throughput Image Scaler
Image scaling is a process of constructing a resized image from a given input image. The constructed image can be smaller, larger, or equal in size, depending on the scaling ratio.

2
Scalable Ultra-High Throughput JPEG-LS Encoder
The UHT-JPEGLS-E core is a JPEG-LS encoder, compliant to ISO/IEC IS 14495-1 | ITU-T Recommendation T.87 standards. It supports encoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams, in 8...

3
Baseline Profile H.264 Encoder H264-BP-E
The H264-BP-E IP Core is an advanced H.264 hardware only encoder that conforms to the ITU-T H.264 Constrained Baseline Profile. The core is also available in ALL-Intra encoding configuration (H264-BPI-E) and supports the real time encoding of video streams up to Profile Level 5.2.

4
High Profiles H.264 Encoder H264-HP-E
The H264-HP-E IP Core is an advanced ITU-T H.264 High profiles hardware only encoder. It supports real time encoding of 4:2:0 and 4:2:2 video streams, in 8-, 10- or 12-bit per component sample depths.

5
Scalable Ultra-High Throughput DSC 1.2b Encoder
The UHT-DSC-E core is a scalable, ultra-high throughput, advanced DSC 1.2b encoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard. It supports encoding of 4:4:4, 4:2:2 and 4:2:0...

6
AES Encryption & Decryption with Fixed Block Cipher Mode AES-C
The AES-C IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key. An included configurable wrapper surrounds the AES-C core and implements its fixed Block Cipher mode of operation.

7
AES Encryption & Decryption with Programmable Block Cipher Mode AES-P
The AES-P IP Core implements the FIPS-197 Advanced Encryption Standard. It can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

8
Authenticated Encryption & Decryption AES-GCM128
The AES-GCM128 IP Core implements the GCM-AES authenticated encryption and decryption, as specified in the NIST SP800-38D recommendation for GCM and GMAC and the FIPS-197 Advanced Encryption Standard. The core can be programmed to encrypt or decrypt 128-bit blocks of data, using 128-, 192-, or 256-bit cipher-key.

9
SHA-1 Secure Hash Function
TheSHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.

10
SHA-256 Secure Hash Function
The SHA256 IP core is a high performance implementation of the SHA-256 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-2. The core is composed of two main units, the SHA256 Engine and the Padding Unit as shown in the block diagram. The SHA256 Engine applies the SHA256 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.

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