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Menta eFPGAs are high-density embedded programmable logic IP digital IPs for use in SoCs or ASICs designed to address various markets and applications.

At Menta, we believe that different problems require different solutions. Therefore, our customers can define the exact resources required for their application.

The table below provide examples of eFPGA that can be provided. Every element of the eFPGA can be defined in numbers: logic cells, MAC, CDSP, SRAM (type and amount) and IOs.

In addition, Menta eFPGA IPs being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.

The eFPGA IP cores are provided as hard IPs (GDSII). Other models are possible, contact us for more information.

Menta eFPGA IPs use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.

Origami Designer is available to help defining the eFPGA IP targeting customer requirements.

For potential customers and partners evaluating Menta's technology, we provide the Menta Starter Pack (MSP).

Block Diagram


  • AI, IoT, Automotive, Cryptography, Space & Defense applications
  • 100% standard cells, fully customisable, ASIC methodology
  • Best Time to Market on any TSMC node and variants
  • Standard scan chain DfT with 100% test coverage
  • Complete, innovative and proven tool suite

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