Welcome to IP - SoC 20 |
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Gabriele Saucier CEO Design And Reuse
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Covid 19 Pandemic effect Virtual, physical of hybrid events?
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Phil Burr Director for Business Transformation Arm Ltd.
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Lowering the Barriers to Innovation for Silicon Startups
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FDSOI Technology Application |
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Philippe Flatresse Product Marketing, FD-SOI Business Unit Soitec
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Live on the Edge with FDSOI
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Eric Hong Senior Director of Engineering Mixel, Inc.
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Leveraging FDSOI Technology for MIPI Applications
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Multicore Architecture |
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Pascal VIVET Scientific Director CEA-LIST
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Energy Efficient 3D Many Core Architecture including Cache Coherency and Power Management
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Interface IP |
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Shikhadevi Katharia Engineer - VLSI Design Silicon Interfaces
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PCIe IP using IEEE UVM Virtual Methods and Parameterization
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Rajeev Huralikoppi IP Application Engineer Silvaco, Inc.
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What's in the new MIPI I3C V1.1 Standard? And what is coming?
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Eric Huang Sr. Product Marketing Manager Synopsys, Inc.
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USB4: A Complex Standard that Simplifies the User Experience
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Zachary Gao DDR Technical Director Innosilicon Technology Ltd
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Innosilicon: Introduction of advanced DDR technology-DDR5/LPDDR5, GDDR6, HBM2E, INNOLINK
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Tony Pialis CEO & President Alphawave Semi
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How DSP is Enabling 224Gbps Serial Links
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Security |
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Neeraj Paliwal VP & GM, Rambus Security Rambus, Inc.
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Security by Design Approach for Semiconductors
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Sean Wang Senior Project Manager eMemory Technology Inc.
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PUF Based Security IPs in IoT and AIoT Applications
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RISC-V |
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Alexander Kozlov CTO CloudBEAR
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RISC-V processor IP product line
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Jan Andersson Director of Egineering Frontgrade Gaisler
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From LEON to NOEL-V processor
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Artificial Intelligence |
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Rahul Thukral Sr. Product Marketing Manager Synopsys, Inc.
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Techniques for Faster, Lower Power AI Algorithm Execution with Foundation IP
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Mark Quartermain Senior Product Manager Arm Ltd.
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Next-generation endpoint AI for IoT with the new Arm Cortex-M55 and Ethos-U55 processors
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Florian Wohlrab Head of Sales for EMEA and Japan Andes Technology Corp.
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AI: Scale from Edge to Server with RISC-V and Linux
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Julian Jenkins CEO and CTO Perceptia Devices
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Using PLLs to simplify DVFS power management in AI and multiprocessor designs
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Tomer Koren Machine Learning System Engineer Ceva, Inc.
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Combining AI in consumer devices using a scalable vector DSP
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5G |
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Fredrik Tillman Head of Integrated Radio Systems Ericsson
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A MIMO radio head at 39GHz targeting 5G NR connectivity inside commercial airplanes
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Cloud and Data Center |
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Mahesh Tirupattur Executive VP Sales, Marketing & Operations Analog Bits Inc.
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Differentiated Clocking, Sensor and Interconnect IPs (5nm and below) for AI/Data Center SOCs
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Craig Forward Sr. Security Products Development Lead Synopsys, Inc.
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Defending the Cloud: Data Protection for High-Performance Computing
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Automotive |
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Rupal Gandhi Sr. Technical Marketing Manager Synopsys, Inc.
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Accelerating Automotive FuSa SoC Design and Certification for ADAS
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Michael Hopkins Founder/CEO CurrentRF
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Mileage Enhancement by Utilizing Wasted Current in Electric Vehicle and e-bike Conversion Systems
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Deepak Shankar Founder Mirabilis Design Inc.
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Architect ECU software and hardware, Next-Gen Automotive Network and gateway design
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Design and verification |
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Pierre GAZULL Business Development and Product Marketing Dolphin Design
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Configurable Software PMU or Low-Power Hardware PMU? Get both with a configurable Power controller IP
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Babun Chandra Pal Member of Technical Staff eInfochips, Inc.
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Modeling Approach of Analog Blocks for Digital Centric Mixed Signal Verification
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Dr. Firas Mohamed VP, Advanced R&D Silvaco, Inc.
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Trusted Variations-aware design solution at advanced nodes!
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Sowmyan Rajagopalan Founder and CTO Thalia
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AMALIA Technology Analyzer - Increasing confidence in Analog & Mixed Signal IP Reuse
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Test Methodology |
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Neil More Engineer - VLSI Design Silicon Interfaces
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Measurable defects detected using Concurrent & Distributed SFF Fault Simulation of PRBS
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Marc Margalef-Rovira Postdoctoral Researcher at IEMN CNRS INP Grenoble
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Testing mmW IP : How solve this SoC design challenge ?
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