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Important Considerations for Verification of CXL Devices

Nicolas Dai - Application Engineer Architect - Cadence Design Systems, Inc.

Biography :

Nicolas has 15+ years of experience in EDA. He started as Applications Engineer at TransEda before co-founding AerieLogic (Formal Verification IP company) in 2004. In 2006 he joined Denali to support worldwide Verification IP customers. He is Cadence Application Engineer Architect since Denali acquisition in 2010 and support customers and closely work with R&D on High Speed Interfaces (USB, PCIe, DP, Ethernet, CXL, UCIe ..) and Memory Model in EMEA.

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