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How to improve the relations between IP consumers and IP vendors and favor IP democratization
Innovation leading to successful product differentiation may come from "small" IP vendors... It can be cumbersome to identify them, to get in touch with them and to assess their IP solutions.
Indeed, there are multiple issues that both IP vendors and customers face.
- IP scouting
How can a consumer promptly find the most suitable or “killer” IP that will allow on-time and successful product launch?- How to find and contact small IP providers, locally or on a global basis?
- How to get IP specification and answers to key IP PPA or other questions (process node for hard IPs, maturity, available views, etc.)
- Would a “customer-driven Search” rather than search on an IP portal be more efficient?
- Maturity and compatibility assessment
- The IP customer will want to promptly assess the compatibility of the IP with his existing design environment.
- The IP evaluation process is often too heavy and time-consuming. Would online access to emulation platforms, FPGA views or prototypes ease that process?
- True IP maturity is sometimes difficult to judge, even if based on silicon reports, verification coverage data or bug occurrence stats; can an industry-wide maturity grading system be defined and deployed?
- Can a user feedback mechanism can be established and published to help other users from a user point of view?
- Can support being assured, especially for complicated analog IPs?
- May a PaaS including evaluation, supporting and quality assurance can be probed?
- Business Negotiation too long
- Vendor screening may be assisted by a reliable (D&R) Ecosystem. Are there geography-specific issues to be addressed?
- Would standardization of business models help?
- Is there space in the market for a centralized control and payment system for IP consideration?
Slides
Mark is General Manager and Founder of Jiatao Industrial Co., Ltd. Located in Shanghai, in which their EDA team focusing on provide IP solutions and EDA tools to its customers in the region. Mark has more than 13 years working experience in IT and business consulting field. For the past two years, he was dedicated on marketing and promoting of high performance analogue and mixed signal IP products in great China region. Prior to the establishment of Jiatao, Mark worked for Swiss consulting firm CH-ina (Shanghai) Co., Ltd. as business consultant and project manager. There his main responsibility is to establish new business operations in China for Swiss and European customers. From year 1996 to year 2004 Mark worked as system analyst and project manager for Cyber Data Processing (CDP) Shenzhen, China.
Mukund is currently the Power Lead for the next generation DataCenter and Cloud Server SOCs. He is chartered with driving Power Efficiency at IP and SOC level, without impacting SOC performance. Mukund has 20+ years of wide ranging cross-domain expertise in SOC hardware design, Engineering Management, IP Program Management and Power/Perf Server designs.
After an initial career in R&D at a research laboratory in Japan, Philippe conducted several management consulting missions in Europe and North & South America for a major US consulting firm.
He joined ST in 1995 in the Corporate Strategic Planning organization where he held several positions in Business Planning & Development. He then led the strategic marketing activities of the Consumer & Microcontroller Group till 2002, when he took the responsibility of the Marketing & Product Strategy activity for the newly formed Imaging Division. In 2007, he joined the Corporate Finance organization, in charge of the intangible asset cycle and led several M&A projects. He was concurrently appointed Site Director for ST and ST-Ericsson's headquarters in Geneva.
Philippe Quinio was born in Versailles, France, in 1965 and graduated with a degree in Telecommunications Engineering from Telecom Paris tech in 1987. Philippe also holds an MBA from INSEAD.
Romain Tourneau is Marketing Manager at PLDA. He has over 10 years of experience in Marketing and Communication and over 5 years of experience in the IP cores Business. He has defined and set up PLDA's Marketing & Communication Strategy which contributed to position the company at the leading edge of the PCIe Market. He holds a Master in Management & Marketing from Kedge Management School, Marseille in France.
PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, CXL, and Gen-Z.
Having spent his early career in AMS chip design and test, Mr. Lerchenmüller then spent 6 years as Application Engineer and AE manager for complex EDA tools such as IMS test-systems and Quickturn HW accelerators/emulators supporting customers in Central Europe and Scandinavia.
Since 2000 he moved into technical Sales and Sales management roles, initially for Cadence emulation solutions, followed by Celestry, and Verisity morphing into an EMEA sales management role for full Cadence verification suite (simulation, testbench, formal and emulation/acceleration tools).
In 2009, he moved from EDA to the emerging IP domain, initially at ARC as VP International sales for EMEA, APAC and Japan, evolving to international roles in Virage and then Synopsys (via M&A). Since 2012 he is back in Cadence, ramping up the emerging VIP and IP business across EMEA with a growing portfolio, organically and by M&A such as Tensilica, Cosmic, Evatronix and lately NuSemi.
He currently works in the Munich office of Cadence Design Systems.
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