In recent years, many hardware security weaknesses arising from integrated circuit hardware vulnerabilities have been exposed. These include lack of virtual machine isolation, secure credential leaks, and privilege escalation. These have put hardware design in the spotlight and raised questions about IC security.

• How is security addressed over the hardware development lifecycle today?
• How should we assess and mitigate security risk in IC design going forward?
• Do we have adequate methodologies, procedures and technology to address it?

Moreover, today’s SoCs and ASICs are not monolithic devices coming from a single source, but rather are composed as a collection of various components, often including 3rd party IPs.

• Does this raise further or different concerns about the management of security risk?
• How much risk does the silicon owner (integrator) inherit?
• What mitigations should be implemented in the IP, and by whom?
• And what residual security concerns exist that should be addressed by the integrator?

Answering these questions should be crucial to all SoC/ASIC integrators, even if their approaches are different. Can an emerging Accellera IP Security Assurance (IPSA) standard provide the solution? Do we even need a new standard here?

Please join this panel discussion to learn the best-practice methods adopted by leading IP integrators and suppliers. What’s different? What’s common? And how this new Accellera initiative creates common ground for the future of IP Security Assurance.

Ireneusz Sobanski is a Senior Validation Engineer at Intel Corporation in Data Center Group. As Formal Validation Lead, he focusses on critical functions validation and is responsible for security mechanisms validation. Ireneusz is a member of Accellera IP Security Assurance WG, where he’s focusing on IP assessment methodology. Ireneusz holds Master degree in Electronics from Silesian University of Technology, Gliwice, Poland. He started his professional career in Evatronix IP (acquired by Cadence in 2013), where as Design and Senior Validation Engineer, he was involved in multiple Soft IP and research projects. Ireneusz is co-author of number of papers and presentations about functional verification, hardware modelling and co-verification.

After receiving his degree in Cryptography, Yann started work at the French DoD, finally reaching the position of Cryptanalysis Team Manager. He then successively joined SCM Microsystems GmbH, managing the security of smart card readers and DVB payTV decoders, then Innova Card, a fabless company providing secure microcontrollers, acting as Chief Security Officer and joined Maxim Integrated as Security Architect, managing all security-related topics including physical protection, cryptography, applications security, and certifications. He’s now Security Architect at SiFive, in charge of defining the platform security at the system level for SiFive RISC-V chips.

Chris has over 25 years of experience in leadership positions within the IT security industry. He was responsible for architecture and implementation of one of the most widely used families of high assurance hardware security modules. Chris’ experience in architecting cryptographic security mechanisms and completing security certifications has made him an expert in identifying vulnerabilities and developing mitigations against a wide range of threats. At Synopsys, Chris uses this experience to design security architectures and perform security assessments within the Solutions Group. In this capacity he has completed security risk assessments of over forty IP titles including security processors, cryptographic accelerators, AMBA components, and PCI Express buses.

Mark Hampton, Safety & Security Consultant for OneSpin Solutions, began his career in digital hardware, working on a wide range of designs, from board to IC and IP. Functional verification captured his interest and spurred a transition from engineering to consulting and training.

The recurring question of how to verify the verification led Mark into the realm of EDA tool research, development, and startup creation, where he developed a keen interest in formal verification methods. Mark joined the team at OneSpin in January 2019 to expand the use of the company’s IC integrity solutions for safety and security applications.

Mark holds a Bachelor of Electrical & Electronic Engineering from the University of Auckland, New Zealand. He is based in France.