Join D&R IP SoC China 21 A worldwide connected Event !!
Co-organized with:
The semiconductor world has to face a worldwide accelerated evolution, never seen before, both in terms of technology evolution (3D Packaging, advanced nodes) as well as new applications (IoT, Artificial Intelligence, Automotive, Security, etc) triggering an increasing demand of Semiconductor resources.
D&R IP SoC Event Series is fully dedicated to IP (Silicon Intellectual property) and IP based Electronic systems. The goal is to promote IP knowledge worldwide sharing as the seed of Electronic Industry permanent innovation.
IP SoC China 21 will be a virtual event with a broad first day program open on September 15th and extended on demand webinars open on September 16th.
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To join the event, you need to be registered.
If not yet done, Register Now !
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Why register?
At the start date upon registration you will be able to listen to their talk and access all material.
You will be able to address any question to the speakers by participating to live on line Q/A sessions at the conference day.
And Good News:
Once registered you will be able to listen to their talk after the event.
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Select the event you wish to watch :
- Virtual Event - Open !
- On Demand Webinar - Open !
- Investment Summit - Open on September 16th
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Introduction
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Gabriele Saucier
CEO
Design And Reuse
with Dagmara Zielinska, Mark Ma
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Innovation in the semi conductor world :Where from? in which area?
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Bulu XU
Chairman
Shanghai Silicon IP Exchange
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Open source of THE IPs - a RISC-V DevBoard case Analysis
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SoC Design
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Stephen Crosher
Strategic Programs Director
Synopsys SLM
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In-Chip Path Margin Analysis for HPC Adaptive Voltage Schemes and Power Optimization
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Dr Doug Ridge
Strategic Marketing Manager
Allegro DVT
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Scalable IP Development for the Surging Semiconductor Industry
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Yin Huang
Sr. Business Development Manager
Imagination Technologies Group Ltd.
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Imagination IP enables the construction of autonomous computing platform
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Richard Oxland
Product Manager
Siemens EDA - Tessent Embedded Analytics
with Gajinder Panesar
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Optimizing Complex AI and ML SoC designs: The Role of System-level Data
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Mo Faisal
President and CEO
Movellus, Inc.
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Intelligent Clock Networks Improve Throughput, Workload Latency and Energy Efficiency for Modern AI SOC's
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Lauri Koskinen
CTO and co-founder
Minima Processor
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It's Energy vs Power that Matters
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SoC Verification
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Qingli He
Synopsys, Inc.
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Simple Scalable and Efficient Automation – Accelerating Verification Closure for Cache Coherent SoC’s
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Analog Design and Memory IP
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Max Wang
FAE
Dolphin Semiconductor
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Powering the next generation of energy efficient and BoM optimized Edge IoT devices with integrated power management and energy-harvesting IP
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Sean Wang
eMemory Technology Inc.
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Secure OTP and Function IP for HPC and AI Applications
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Jack Guedj
CEO
Numem
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A 2MB 16nm sub 5ns Reads MRAM-based Memory IP Core
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Lisa Yang
Business Consultant
Agile Analog
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Flexible, configurable, process and foundry agnostic analog IP design the Agile way
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Interface IP
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Yemin Qiu
Sales Director
Corigine Inc.
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Corigine USB Interface IP with high performance and good compatibility
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Harry Chan
Founder & CEO
eTopus Technology Inc.
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A 1-112G/64bps PAM4 ADC/DSP-based Multi-protocol SerDes IP for Data Center, 5G and AI applications
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Miao Wei
Sr. Principal Engineer, Multimedia SoC Platform
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
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VeriSilicon FLEXA Enables Low Latency, Low Power DDR-less Applications
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Tony Chen
Director of Marketing, Design IP
Cadence Design Systems, Inc.
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Pushing the envelope for hyperscale designs with PCI Express 5.0 and 6.0: Bringing PAM4 to PCIe
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Haopeng Liu
Technical Support Director
AkroStar Technology Co., Ltd.
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Design and implementation of DDR interface with high performance, low power and high reliability
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Eunice Rao
Brite Semiconductor
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Prospects and Technology of High-Speed Interface IP
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Alex Chen
Senior Sales Director
OpenFive
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D2D IP for AI SoCs in Data Center and HPC Applications
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Zachary Gao
CTO
Innosilicon Technology Ltd
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Domestic one stop high speed interface IP and high performance computing chip customization solution
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Tony Pialis
CEO & President
Alphawave Semi
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How DSP is Enabling 224Gbps Serial Links
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RISC-V Ecosystem
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Evans Yang
Executive VP
PUFsecurity
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How PUFiot and RISC-V Realize Secure SoC
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Processor IP
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Tina Xiang
Codasip GmbH
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Codasip symmetric multiprocessor with coherent memory system based on A70X
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Steven Brightfield
Chief Marketing Officer
Siliconarts, Inc.
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Turbocharging an ARM Mali GPU for real-time Ray Tracing
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Artificial Intelligence
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Wendy Chen
IP and Ecosystem Sales Group Director of Asia-Pac & Japan
Cadence Design Systems, Inc.
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Cadence Tensilica On Device AI IP Solutions for Broad Market Use Cases
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Security
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Meng-Yi Wu
R&D Director
PUFsecurity
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Securing the Supply Chain through Hardware Root of Trust
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Cloud and Data Center
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Raymond Su
Country Manager of Greater China
Rambus, Inc.
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Emerging Compute Architectures for the Evolving Data Center
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Matthew Ma
Security IP FAE
Synopsys, Inc.
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Defending the Cloud: Data Protection for High-Performance Computing
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Connectivity
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William Tseng
Arteris IP
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Automating Hardware-Software Interface (HSI) Creation Using NoC Interconnect and IP Deployment Technology
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Ravi Thummarukudy
CEO
Mobiveil Inc.
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Compute Express Link™ (CXL™) – New breakthrough interconnect technology for Data Center Applications
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Design and Verification
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Yuxiang (Gary) Mu
Physical Design Engineer
Movellus, Inc.
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Intelligent Clock Networks Improve Throughput, Workload Latency and Energy Efficiency for Modern AI SOC's
Duration : 30min
Believe it or not, clock distribution networks are incredibly inefficient. Learn three simple questions executives can ask to reveal these inefficiencies. Hint: It's not an engineering issue; it's an architecture and IP issue. Architecture innovation has happened in Processing Elements, data delivery (NOCs), and memory, but clocks are still buffers and wires. Find out how adding intelligence and architecture innovation to the clock distribution network can eliminate power supply droop (workload), reduce PVT/OCV effects (throughput/power), and reduce/eliminate current noise (power).
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Donghui Hou
General manager of Sales Department
Corigine Inc.
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MimicPro - Prototyping System for SOC and IP Subsystem Verification
Duration : 40min
Corigine has developed the world-leading SoC prototyping and simulation system MimicPro in the highly specialized EDA field. It is the third generation of integrated prototyping and simulation, and FPGA-based hardware acceleration platform. It has won the purchase orders from several major domestic and foreign IC design customers. The first 8 sets of MimicPro products have been delivered to a domestically renowned semiconductor company on June 21, 2021. It has also been highly recognized by our partner Xilinx.
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Interface IP
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Haopeng Liu
Technical Support Director
AkroStar Technology Co., Ltd.
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Design and implementation of DDR interface with high performance, low power and high reliability
Duration : 45min
With the rapid development of hot applications such as cloud computing, 5G, Internet of Things, and artificial intelligence, the demand for DDR DRAM has greatly increased. As the most critical module for DDR technology, the market demand for DDR PHY has also grown rapidly. AkroStar’s DDR PHY IP has achieved technological innovation and breakthroughs in high-performance IO, high-reliability training, multi-frequency fast switching, SI/PI modeling, etc., and fully empowers chip DDR interface design.
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AI and Data Center
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Raymond Su
Country Manager of Greater China
Rambus, Inc.
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Emerging Compute Architectures for the Evolving Data Center
Duration : 45min
As the world has become increasingly connected, processing continues to evolve from the familiar cloud computing paradigm. The vast profusion of IoT devices has contributed to the exponential rise in data volume. Greater intelligence is moving to the edge of the network and to the end points themselves to provide greater, real-time functionality. The implications for global network infrastructure are profound and there are significant developments in computing architectures which will shape the future data center.
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The Expanding Universe of MIPI Applications: New Use Cases Drive Higher Display Performance
When : September 15th, 10am, California Time (PDT)
How : Click on Join the panel - Register ahead
Organized by Rambus, Inc.
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The huge success of MIPI display interface technology embedded in billions of mobile phones annually has made it an attractive solution for display interconnects across a growing number of market applications. These new applications bring new performance requirements: higher resolutions, greater numbers of displays, and more. This panel will discuss the emerging market trends and design challenges, and how technical innovations can enable MIPI DSI-2 solutions that provide the performance needed in next-generation displays.
with the participation of : - Joe Rodriguez, Product Marketing Manager, Rambus
- Simon Bussières, Product Manager, Hardent
- Ashraf Takla, President and CEO, Mixel
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Joe+Rodriguez
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Simon+Bussières
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Ashraf+Takla
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Post-covid World and IoT Security Challenges
When : September 15th, 4pm, California Time (PDT)
How : Click on Join the panel - Register ahead
Organized by PUFsecurity
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In face of Covid-19, new IoT trends, such as the need for remote work, has led to even more connectivity in our daily lives. With the acceleration in connectivity comes more security challenges for the post-Covid world.
Keeping these issues in mind, companies must be prepared for how to deal with the increasing need for IoT deployment and security. This panel will discuss some of these issues mentioned above and explore what is needed in a system to secure the connected world right from design.â
with the participation of : - Tom Katsioulas, Board Chair, GSA Trusted IoT Ecosystem Security (TIES)
- Meng-Yi Wu, R&D Director, PUFsecurity
- Luis Ancajas, Director of IoT Solutions, Micron
- Sean Wang, Senior Marketing Manager, eMemory
- Albert Jeng, Security Consultant, PUFsecurity
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Tom+Katsioulas
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Luis+Ancajas
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Albert+Jeng
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Meng-Yi Wu
PUFsecurity
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Sean Wang
eMemory Technology Inc.
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