Andes' Core has RISC-V Vector Instruction Extension

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Andes' new processor cores enable scalability by delivering RVV instruction extension and new memory subsystem. The company claims to be the first to deliver a core with the extension to a customer.

eetimes.com, Dec. 09, 2019 – 

Andes Technology has released the AndesCore 27-series CPU cores, which it claims are the first licensable RISC-V core to deliver to a production licensee the RISC-V vector instruction extension (RVV). It has also re-architected the memory subsystem to sustain memory bandwidth and efficiency.

Andes has delivered the core to its first licensee, with production release slated for Q1, 2020. Charlie Su, CTO and EVP of Andes Technology, told EE Times the first customer will use the new core for a datacenter AI engine. The customer plans to reveal itself, along with details of how it's using the Andes core, at the RISC-V Summit in San Jose, California this week.

The president of Andes Technology, Frankwell Lin, said, "The RVV extension boldly takes RISC-V beyond any licensable processor core technology into the hottest markets today, and our licensee's confidence in the R&D team enables Andes to be the first to deliver on this ambitious vision. The team has worked together from specification to delivery in less than nine months."

The advent of AI, AR/VR, computer vision, cryptography, and multimedia processing all require complex computation of large volume of matrix data. Unlike other vendors' advanced SIMD, which has a narrow range of performance dictated by their architecture control, the RVV specification envisions a powerful instruction set with scalable data sizes, flexible microarchitecture implementations, and leaves memory subsystem decisions open for system level optimization. With the 27-series CPU cores, Andes said it delivers this unprecedented performance and flexibility to the RISC-V community and for the first time, enables RISC-V cores to fill a void in applications other vendors have not been able to reach.

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