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RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G...
More stuff that'll get under Arm's skin
theregister.co.uk, Dec. 10, 2019 –
SiFive is now willing to license RISC-V cores that support the open-source ISA specification's still-in-draft vector extension instructions.
These software-generated cores, dubbed the SiFive Intelligence series with the first being the VI2, are configurable by system-on-chip designers: you can control the size of the supported vectors by tweaking the VLEN parameter. The default is 512 bits, and can run up to 4,096. Vector math is useful for accelerating machine-learning algorithms, signal processing, and so on – pretty much all modern microprocessors feature this sort of stuff. The Intelligence cores can execute software in- and out-of-order, too.
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