Advanced Packaging For More-than-Moore Era

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Chip scaling has reached the point of diminishing returns. The next phase of semiconductor innovation will focus on integrating a myriad of chip components. Our Advanced IC Packaging Special Project looks at the challenges and the opportunities...

www.eetasia.com, Dec. 28, 2020 – 

Semiconductor packaging has never been more critical. What's driving the next generation of IC packaging? What does the ongoing disruption in multi-die advanced packaging look like?

Our Special Project examines advanced IC packaging technologies, looking at the road ahead for a critical manufacturing capability that could help revive flagging western chip makers.

Transistor scaling is running out of steam, making advanced IC packaging another manifestation of engineering black magic. Layer after layer of transistors are being stacked in 2.5D and 3D packages while technology behemoths like Intel Corp and Taiwan Semiconductor Manufacturing Co. strive for tighter integration between process and packaging technologies.

In the "More than Moore" era, process engineers need to understand next-generation integration technologies while back-end engineers build extremely dense packages. System-level design engineers also need more clarity on this tectonic shift in the semiconductor world.

However, it seems there is little understanding of how this transition will unfold. For instance, what's on the die versus what's on the package?

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