FD-SOI Boosts Operating Frequency And Reduces Power Consumption

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

Paper presented at the ISSCC 2021 shows how new adaptive back-biasing technique overcomes integration limits in chip design flows

www.electronicsforu.com, Mar. 03, 2021 – 

CEA-Leti and Dolphin Design have developed an adaptive back-biasing (ABB) architecture for Fully Depleted Silicon on Insulator (FD-SOI) chips that can be seamlessly integrated into the digital design flow with industrial-grade qualification, overcoming integration drawbacks of existing ABB techniques.

FD-SOI is a technology that allows the biasing of the transistor's body to act as a back gate. Unlike conventional bulk technology, FD-SOI enables a wide voltage range of body bias. This permits compensating for process, voltage and temperature (PVT) variations by controlling the threshold voltage. For example, in switch operations, when the switch is on, the body bias is changed to reduce the on-resistance by reducing threshold voltage and allowing more current to pass. That accelerates the circuit. In the off state, the body bias is changed to raise the off-resistance by increasing the threshold voltage, consequently reducing the leakage current. This shows that FD-SOI technology can be used either to accelerate the design or reduce the leakage power.

click here to read more...

 Back