Will Fan-Out Wafer-Level Packaging Keep Moore's Law Valid?

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www.eetimes.eu, Mar. 22, 2021 – 

Moore's Law in process technology is on its last legs, so advanced packaging is taking up the baton. Advanced techniques such as fan-out wafer-level packaging (FOWLP) allow increased component density, boost performance, and help solve chip I/O limitations. The key to using such techniques successfully, however, is to include the package in the chip design from the start.

For decades, semiconductor processing technology has steadily pushed feature sizes down from tens of microns to single-digit nanometers, effectively doubling component density every 18 months. At the same time, however, design and fabrication costs have risen, threshold margins have narrowed, and a host of other challenges have appeared to impede further progress. Furthermore, increased transistor density in individual chips has created problems in interconnecting them, such as limiting I/O pin count and chip-to-chip interconnect speed.

These limitations are proving especially problematic in applications such as AI edge and cloud systems that need massive amounts of high-bandwidth memory. To address these issues as well as to continue improving component density, the industry has developed several advanced packaging technologies that allow multiple chips to interconnect in a compact, high-performance package that functions on a board as a single component.

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