Samsung Foundry tapes out 3nm GAA chip

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The tapeout of a mullti-subsystem SoC uses Synopsys Fusion Design Platform for Samsung Foundry's 3nm Gate-all-around (GAA) transistor process technology

eenewseurope.com, Jun. 28, 2021 – 

Taking on TSMC at the leading edge of process technology, Samsung Foundry has taped out a 3nm chip that uses its Gate-all-around (GAA) transistor architecture.

This requires a different set of design and qualification tools from the FinFET transistor structures used by TSMC and Intel, so Samsung used the Fusion Design Platform from Synopsys. The physical design kit (PDK) for the process was released in May 2019 and tools were qualified on the process last year.

The tapeout was the culmination of an extensive collaboration between Synopsys and Samsung Foundry to accelerate the delivery of a highly optimized reference methodology for the GAA process.

The reference design flow includes an integrated and golden-signoff-enabled RTL-to-GDSII design flow coupled with golden-signoff products. The flow is aimed at customers wanting to use the 3nm GAA process for chips in high-performance computing (HPC), 5G, mobile and advanced, artificial intelligence (AI) applications.

"Samsung Foundry is at the heart of fueling the next phase of industry innovation with our continued process-technology-based evolutions to meet the growing demands of both specialized and broad-market applications," said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics. "Our latest, advanced 3nm GAA process has benefited from our extensive collaboration with Synopsys, and the accelerated readiness of the Fusion Design Platform to enable the efficient realization of the 3nm process' promise, is a testament to the importance and benefit of these key alliances."

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