RISC-V wireless chip with Adaptive Body Bias reaches pW power

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CSEM and USJC have developed an ultralow power RISC-V wireless chip with standby power as low at 1pW/bit by using adaptive body bias.

www.eenewseurope.com, Aug. 17, 2021 – 

Researchers in Switzerland and Japan have developed a RISC-V wireless system on chip with anactive power consumption as low as 10µA and an ultra low power standby mode that consumes just 1pW/bit.

The SoC developed by CSEM and United Semiconductor Japan (USJC) operates in near-threshold region at 0.6 V and combines user-configurable power management unit (PMU) and bias generator circuits to implement automatic adaptive body bias (ABB) regulation over process, voltage and temperature (PVT)

"This could mean, for example, keeping the power requirement constant between generations of devices, such as smartphones, which are the same size as the phones we used ten years ago but have 100 times more features. Or using a different kind of power supply, like a tiny solar panel, to run a device," says Stéphane Emery, head of system-on-chip research at CSEM.

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