Open standard for RISC-V verification is announced at DVCon

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www.electronicsweekly.com, Mar. 03, 2022 – 

Components based on the open standard can be re-used across design teams and even across different companies, proposed Github. "In short, standards such as RVVI make re-use possible for RISC-V processor design verification."

RVVI address the RTL of the core's microarchitecture to provide tracing capabilities. The RVVI-VLG (Verilog interface) is defined in SystemVerilog and includes capabilities for use with cores with asynchronous iterrupts and debug modes.

Another area addressed by the standard is to verify a RISC-V core using a device under test against a reference model, encompassing all the architectural features and options including full asynchronous operation. The RVVI-API is a C/C++ API which can be used with C/C++ test benches and has a SystemVerilog DPI (deep packet inspection) wrapper for SystemVerilog test benches.

The third area addressed by RVVI is the reference model design verification subsystem. The RVVI-VPI covering timers, interrupts, debug, random event generators and printer/log/uart capabilities is still being developed.

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