Ashling to supply toolchain for MIPS RISC-V cores

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Processor core developer MIPS is working with long term partner Ashling on development tools for its RISC-V cores. MIPS has pivoted to developing RISC-V cores since it emerged from bankruptcy a year ago. While still supporting the licensed MIPS architecture where Ashling also provides tools, MIPS has used its Core

www.eenewseurope.com, Mar. 29, 2022 – 

Processor core developer MIPS is working with long term partner Ashling on development tools for its RISC-V cores.

MIPS has pivoted to developing RISC-V cores since it emerged from bankruptcy a year ago. While still supporting the licensed MIPS architecture where Ashling also provides tools, MIPS has used its Core Framework Platform for cores using the RISC-V open source instruction set architecture. This is seen as a migration path to a new instruction set for existing and new chip design customers.

RiscFree is Ashling's Integrated Development Environment (IDE) including a compiler and debugger for RISC-V based development. This will include support for both code development and debug on MIPS RISC-V IP cores and includes multi-core and multi-cluster support, Linux debug awareness, real-time trace support and cache awareness. It also comes with a range of Ashling hardware probes supporting debug and trace. In addition, a targeted and optimised GCC toolchain is included and fully integrated into the RiscFree IDE.

Ashling has design centres in Limerick, Ireland, and Chennai, India, with sales and support offices in Europe, Asia Pacific, the Middle East and America. It supports Synopsys ARC, ARM, MIPS, IBM's Power Architecture and RISC-V in RiscFree, and was the first company to bring tools to the market supporting heterogenous debug of RISC-V cores along with cores from other vendors.

"We are excited to see MIPS, one of the first companies to bring a RISC based architecture to the market back in the 1980s, now expanding to offer RISC-V ISA compliant cores. We've a long history of working together and believe the support of our market-leading RiscFree Toolchain will help in the rapid market adoption of their MIPS RISC-V ISA cores," said Hugh O'Keeffe, CEO of Ashling.

"We are delighted to have Ashling RiscFree support for our RISC-V ISA IP cores. Our engineering teams have worked closely together developing the toolchain in parallel with the core IP and believe this can result in rapid time-to-market for our end customers," said Don Smith, Vice President of Engineering at MIPS.

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