Samsung Leads Chip Industry with Nanochip Production

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www.eetimes.com, Jul. 01, 2022 – 

Samsung Electronics claims a world first as it plans to start production of chips using a new nanosheet transistor architecture at the industry-leading 3nm process node.

The world's second-largest chip foundry implemented the nanosheet technology, also known as gate-all-around (GAA), leading top rival Taiwan Semiconductor Manufacturing Company (TSMC), which aims to adopt the technology for production in 2025. TSMC plans to kick off production of 3nm chips later this year.

Nanosheet technology promises to exceed performance limitations of FinFET, the current 3D-chip process used by Samsung and TSMC at the 7nm and 5nm nodes. Nanosheet is expected to improve power efficiency by reducing chip supply voltage levels, while also enhancing performance by increasing drive-current capability.

Samsung will initially use the nanosheet architecture to produce chips for high-performance, low-power computing applications followed by mobile processors, the company said in a press statement.

"We continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry's first high-K metal gate, FinFET, as well as EUV (extreme ultraviolet lithography)," said Siyoung Choi, president of Foundry Business at Samsung Electronics. "We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology."

Samsung said it has developed nanosheets with wider channels, which enables higher performance and greater energy efficiency compared to rival GAA technologies using nanowires with narrower channels. The company expects to adjust the channel width of nanosheets in order to optimize power usage and performance to meet various customer needs.

GAA is expected to yield power, performance, and area (PPA) benefits. Compared with 5nm, Samsung said the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23%, and reduce area by 16%. The second-generation 3nm process will reduce power consumption by up to 50%, improve performance by 30%, and reduce area by 35%, according to the company.

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