French secure element processor uses RISC-V

www.eenewseurope.com, Oct. 12, 2022 – 

French processor designer Tiempo Secure has developed secure IP based on the RISC-V open instruction set.

The TESIC Secure Element IP uses the RV32IMCB 32bit RISC-V specification to adopt a standard architecture alongside its existing proprietary CPU architecture. This will make integration easier for developers who can now use standard development tools, making the integration of its TESIC security elements into system on chip designs faster and easier.

The secure elements are used in chips for the authentication on networks with integrated SIM (iSIM/iUICC), payment (EMVCo), government or private identification, web authentication (FIDO 2), smart car access, and communication with autonomous vehicles (V2X HSM).

The company is based in Grenoble, France, and also becomes a Strategic Member of RISC-V International, which helps to guide the development of the technology.

"Joining RISC-V International represents a milestone for Tiempo Secure. Not only will we be able to keep on delivering secure products to our customers, but we are now making it easier to implement our products into their own System-on-Chips and software," said Serge Maginot, CEO of Tiempo Secure.

As Tiempo Secure is a well-established security expert, its TESIC Secure Element IP products are certification ready. Tiempo Secure TESIC Secure element IP has been integrated into System-on-Chips that have passed Common Criteria EAL 5+ certification. Also, Tiempo Secure commits to bringing extensive support to its integrators ensuring that they obtain security certification.

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