'First' RISC-V CPU certified compliant with ISO 26262

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Andes Technology has introduced safety-enhanced RISC-V CPU intellectual property, claiming it to be "the first to certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications".

www.electronicsweekly.com, Oct. 17, 2022 – 

SGS-TÜV Saar audited the core, called N25F-SE, and certified it to ASIL B according to ISO 26262 including Parts 2, 4, 5, 8 and 9, said Andes.

It is a 32bit RISC-V core that supports standard IMACFD extensions, integer, single precision floating point and double precision floating point instructions, as well as Andes V5 extensions, intended to boost performance and reduce code size.

Balancing operating frequency and gate count, a five-stage pipeline has been implemented, and "N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions", said Andes.

To assist design teams in certify their SoCs to ISO 26262, N25F-SE comes with a safety package including safety manual, safety analysis report (FMEDA and more, said Andes) and development interface outline.

It sees ASIL B level functional safety as applicable to dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS and window control; pointing out that an ASIL B processor saves power compared with an ASIL D processor, as the latter needs dual-core lock-step and therefor doubles core size.

Following N25F-SE, a version with DSP/SIMD and bit manipulation extensions ('D25F-SE') is scheduled for early 2023.

Andes was founded 17 years ago and is based in Hsinchu Taiwan.

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