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Solutions Disclosed at RISC-V Summit: Security, Verification, and More
At this year's RISC-V Summit, stakeholders rolled out solutions revolving around verification, security, and software-defined SoCs.
www.allaboutcircuits.com, Dec. 15, 2022 –
This week is the annual RISC-V Summit in San Jose, CA, where many of the major players in the industry get together to share technology and discuss the future of the RISC-V industry. Building off of the moment of the numerous RISC-V announcements in 2022, this year's summit has had no shortage of exciting announcements.
Among these, recent announcements from Imperas, XMOS, and Codasip have been of particular interest. In this article, we'll examine each of these releases to understand the current and future direction of the RISC-V industry.
Imperas RISC-V Verification Tool Updates
The first set of news coming from this week's RISC-V summit comes from Imperas regarding its RISC-V verification software.
Design verification is particularly important in RISC-V since the open-sourced nature of the standard means that anyone can contribute to IP. Hence, there is the potential for errors or inconsistencies to be introduced into the design if it is not carefully managed.
To address this, Imperas has announced a new set of updates to its ImperasDV software, which is a leading RISC-V design verification software tool. Amongst these updates includes the inclusion of riscvISACOV IP extensions, which is a set of SystemVerilog functional libraries, as well as the inclusion of architectural validation test suites.
These new test suites include RV32E, RV64E, Zc, and Zmmul specifications, each of which helps ensure that hardware implementations match the expectations of the RISC-V software ecosystem.
With these new additions to ImperasDV, Imperas hopes to enable RISC-V designers with the tools and flexibility necessary to reliably develop the next generation of RISC-V designs.
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