BoW Strengthens Pathway to Chiplet Standardization

This week's Chiplet Summit underscores the rapid evolution of the ecosystem around multi-die chip design. Such a gathering of experts emphasizes how this area has quickly emerged as a critical part of every leading-edge silicon development strategy, an inflection point in a roadmap long guided by Moore's Law and now being driven to find innovation methods to continue the required scaling.

www.eetimes.com/, Jan. 26, 2023 – 

The success of chiplet architectures will depend on the interconnect between the chiplets. It must provide massive bandwidth and great energy efficiency, and it must require minimal beachfront and die area. Standards and interoperability are key, and initiatives like Universal Chiplet Interconnect Express (UCIe) and JEDEC are putting important processes in place to guide development efforts.

The state of die-to-die interconnects

Today, there are two fundamental approaches to achieving the technology objectives mentioned above.

The first approach is to simply extend the number of interconnects–copper lines–between chiplets, using advanced packaging technologies like silicon interposers or embedded silicon bridges. These links can be driven by large inverters but mostly at relatively lower rates–about 1 to 16 Gbps per line. They get higher bandwidth by leveraging very fine bump and line pitches, allowing huge numbers of lines between chiplets.

Unfortunately, advanced packaging is very complex to fabricate and assemble at the large sizes required by high-performance systems-in-package. Wafer testing to screen the chiplets–with those extreme pitches–for known-good dies is limited and leads to yield issues. It is proprietary, limiting the ability to move designs between fabs. And the very short reach–2 to 3mm–of advanced packaging interconnects between chiplets can greatly complicate thermal design, especially if some chiplets, such as HBM DRAM dies, must be protected from high temperatures of hot processor chips next to them.

The second approach is to use SerDes and high-speed serial transceivers to move data at very high rates–16 to 64 Gbps per line. This can drastically reduce the number of interconnect lines necessary for a given aggregate bandwidth. And with relaxed pitches and properly tuned transceivers, it can work over organic substrates as well as over silicon interconnects.

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