Renesas develops technologies for automotive gateway SoCs

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Renesas Electronics Corporation has developed four technologies for system-on-chip (SoC) devices for in-vehicle communication gateways. These SoCs are expected to play a crucial role in defining the next-generation electrical/electronic (E/E) architecture in automotive systems.

www.eenewsembedded.com/, Feb. 22, 2023 – 

SoCs for automotive gateways must provide both high performance to implement new applications such as cloud services, and low power consumption when they are not in use. They also need to deliver fast CAN response to support instant start-up. Additionally, these SoCs need to provide power-efficient communication technology that enables network functions as a gateway using limited power and security technology to enable safe communication outside the vehicle.

To meet these requirements, Renesas has developed (1) an architecture that dynamically changes the circuit operation timing to match the vehicle conditions with optimized performance and power consumption, (2) fast start-up technology by partitioning and powering essential programs only, (3) a network accelerator that achieves a power efficiency of 10 Gbps/W, and (4) security technology that prevents communication interference by recognizing and protecting vital in-vehicle communication related to vehicle control.

Architecture

Communication gateway SoCs need to deliver processing performance exceeding 30,000 Dhrystone million instructions per second (DMIPS) when running, while also keeping standby power consumption to 2 mW or less in order to maintain battery life. Typically, high-performance SoCs also have high power consumption in standby mode, while low-power SoCs with small standby power consumption have performance issues. To resolve this tradeoff, Renesas combined in a single chip a high-performance application system and a control system optimized for ultralow standby power consumption. The new architecture controls the power supplies of these two subsystems and changes the timing of circuit operation to achieve an optimal balance between performance and power efficiency. This results in higher performance during operation and lower power consumption during standby.

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