- Synopsys ramps up collaboration with Taiwan's TSMC on A16 process
- SMIC Q2 revenues to take 6% hit due to tool maintenance and validation issues
- EDA Companies Throw Support Behind TSMC's New A14 Process
- Rapidus Starts Path to Advanced Chipmaking in Japan Government-backed startup's 2-nanometer pilot production gets underway
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
IP-SOC DAYS 2025 IP-SOC DAYS 2024 IP-SOC DAYS 2023 IP-SOC DAYS 2022 IP-SOC DAYS 2021 IP-SOC 2024 IP-SOC 2023 IP-SOC 2022 IP-SOC 2021
|
|||||||
![]() |
|

TSMC's 3-nm progress report: Better than expected
- Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design (May. 16, 2025)
- Semidynamics: From RISC-V with AI to AI with RISC-V (May. 16, 2025)
- TSMC Board of Directors Meeting Resolutions (May. 16, 2025)
- Arm Evolves Compute Platform Naming for the AI Era (May. 16, 2025)
- Secafy Licenses Menta's eFPGA IP to Power Chiplet-Based Secure Semiconductor Designs (May. 15, 2025)
- See Latest News>>
TSMC, which vowed to kickstart its 3-nm process node in the second half of 2022, barely made it by cutting the ribbon on this cutting-edge manufacturing node on December 29 at its expanded fabrication unit in Southern Taiwan Science Park (STSP). Nearly six months after Samsung began 3-nm chip production based on gate-all-around (GAA) technology, TSMC has successfully conducted its full-node advance from 5-nm to 3-nm chip manufacturing process based on tried-and-test FinFET transistor architecture.
www.edn.com/, Mar. 08, 2023 –
According to media reports, Apple has secured 100% of the initial supply of N3, TSMC's first-generation 3-nm process, starting as a baseline. The early reports show that the N3 process yield could be as high as 80%. Next, TSMC plans to move to a more advanced 3-nm version, N3E, in the second half of 2023. That's when other TSMC customers–AMD, Intel, and Qualcomm–plan to adopt the 3-nm process for their chips.
N3, which uses an ultra-complex process with 24-layer multi-pattern extreme ultraviolet (EUV) lithography, is denser and thus offers higher logic density. On the other hand, N3E, which uses a simpler 19-layer single-pattern technology, is easier to produce and is less expensive. It'll also use less power and clock higher compared to the baseline N3 process.
TSMC's CEO C. C. Wei expects the 3-nm manufacturing process to be worth more than $1.5 trillion business within five years of volume production. For now, however, N3 wafers cost around $20,000 compared to $16,000 for TSMC's 5-nm node called N5. That's partly why chip developers besides Apple are known to sit on the sidelines while waiting for the more economical N3E process node.