www.design-reuse-embedded.com
Find Top SoC Solutions
for AI, Automotive, IoT, Security, Audio & Video...

Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies

Cadence 112G-LR SerDes silicon proven in GUC's HBM3/GLink/CoWoS platform

www.cadence.com/en_US/home.html, Apr. 26, 2023 – 

SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC). This milestone in the companies' ongoing and successful collaboration solidifies Cadence's leadership in high-performance connectivity IP for the high-bandwidth, high-reliability products that power the most advanced cloud data centers.

GUC's big-die CoWoS platform represents real-world CPU, GPU, AI, and networking chips by integrating multiple instances of the Cadence 112G-LR SerDes with a 7.2Gbps HBM3 controller and PHY, as well as a GLink-2.5D die-to-die IP in the TSMC N7 process. Cadence collaborated with GUC on the interposer design to meet the strict high-speed signal integrity (SI) and power integrity (PI) requirements of 112G-LR SerDes signaling through silicon (CoWoS-S) and organic (CoWoS-R) interposers. The 112G-LR SerDes has been validated in the GUC CoWoS platform, demonstrating excellent performance and robustness in large-scale AI/HPC/networking chip conditions.

"Our AI/HPC/networking platform on TSMC's CoWoS® technology meets high-power and high-speed requirements at the system level and demonstrates our industry leadership in delivering complete advanced packaging solutions," said Igor Elkanovich, CTO at GUC. "Cadence's robust, production-quality 112G SerDes was instrumental in allowing us to unleash new potential for scalable, multi-die AI, HPC and networking solutions."

"The successful demonstration of the Cadence 112G-LR SerDes in GUC's platform using TSMC's CoWoS technology is a great example of design ecosystem collaboration on 2.5D multi-die packaging solutions," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Cadence's leading IP solutions together with TSMC's advanced technologies enable system-level innovations for AI/ML, HPC and networking applications."

click here to read more...

 Back

Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.