Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard

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Highlights:

• The Cadence Integrity 3D-IC platform, a complete solution certified for all the latest TSMC 3DFabric ™ offerings, combines system planning, packaging, and system-level analysis, providing a seamless design creation and signoff flow
• Flows fine-tuned to support 3Dblox ™ , which speeds 3D front-end design partitioning in complex systems
• Cadence and TSMC technologies improve design quality and accelerate turnaround time for 3D-ICs used in 5G, AI, hyperscale computing, IoT and mobile applications

www.cadence.com/en_US/home.html, Apr. 26, 2023 – 

SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced new design flows based on the Cadence® Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC's latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®) and System-on-Integrated-Chips (TSMC-SoIC® ) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.

The Cadence Integrity 3D-IC platform combines system planning, packaging, and system-level analysis andis a complete solution certified for use with the TSMC 3DFabric and the 3Dblox 1.5 specification. The flows based on this platform incorporate several new features like 3D routability-driven bump assignment and hierarchical bump resource planning. 3Dblox, which is inherently supported by the Integrity 3D-IC platform, provides a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus™ IC Power Integrity Solution and Celsius™ Thermal Solver system analysis tools; extraction and static timing analysis via the Cadence Quantus™ Extraction Solution and Tempus™ Timing Signoff Solution; and system-level layout versus schematic (LVS) checks via the Cadence Pegasus™ Verification System.

"3D-IC technology is key to meeting the performance, physical size, and power consumption requirements to enable next-generation HPC and mobile applications," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "By continuing our collaboration with Cadence, we're enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows that support our 3Dblox standard, so they can significantly improve 3D-IC design productivity and speed time to market."

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