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Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies

www.cadence.com/en_US/home.html, Apr. 25, 2023 – 

SAN JOSE, Calif.– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a node-to-node design migration flow based on the Cadence® Virtuoso® Design Platform compatible with all TSMC advanced nodes, including the latest N3E and N2 process technologies. This new generative design migration flow was jointly developed by Cadence and TSMC to provide a simplified and automated approach to migrate custom and analog IC designs among TSMC's process technologies. Customers already using the flow have successfully reduced migration time by 2.5X when compared with manual migration.

The Virtuoso Design Platform automatically migrates schematic cells, parameters, pins and wiring from one TSMC process node to another. The Virtuoso ADE Product Suite's simulation and circuit optimization environment then tunes and optimizes the new schematic to ensure the design achieves all required specifications and measurements.

Cadence and TSMC customers can then automatically recognize and extract groups of devices in an existing layout and apply them to similar groups in the new layout, thanks to the Virtuoso Layout Suite's generative design technology using templates, TSMC's analog-mapping and routing technologies in the Virtuoso Design Platform.

"As application requirements grow, many TSMC customers are looking to migrate legacy IC designs to our more advanced nodes, such as N3E and N2, to take full advantage of higher performance and lower power benefits of the latest TSMC advanced technologies," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our ongoing collaboration with Cadence has resulted in enhanced PDKs and methodologies that simplify and accelerate the design migration process, ultimately speeding time to market."

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