Upgrade Your Display and Camera SOC's with proven MIPI C-D Combo PHY and CSI / DSI Controller IP Cores for both Tx and Rx

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May. 15, 2023 – 

15^th May 2023. – T2M^IP, the world's leading independent semiconductor IP cores provider and technology experts, is pleased to announce the immediate license availability of its partner's MIPI Alliance-approved semiconductor - MIPI C-D Combo Tx/Rx PHY IP cores. It provides a high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, AI, and IoT applications. The PHY is compliant with the MIPI C- D combo Tx/Rx PHY IP protocol and operates at a 10Gb/s aggregate data rate in 4 lanes. Supporting low-power state modes enables the IP to achieve low-power consumption at maximum speed, improving the energy needs of devices powered by batteries. The MIPI C-D Combo Tx/Rx PHYs with MIPI CSI/DSI Controllers deal with significant MIPI display and camera benchmarks.

MIPI C-D Combo Tx and Rx PHY IP cores with matching Controllers are getting popular in the market as it enables rapid deployment/growth for mobile, AR/VR, and automotive displays and this optimized solution is now available for your futuristic display products. MIPI C-PHY/D-PHY combination IP is a physical layer with a high frequency, low power, and low cost. It can be used as a MIPI transmitter or receiver, and it supports both camera and display interfaces.

MIPI CSI Controller IP core is compliant Standard v3.x, v2.x, v1.x, and MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x, and MIPI C-PHY V1.x, with C-PHY capability of 3 Gbps per trio and 17Gbps in three Trios. This can reach up to 2.5 Gbps per D-PHY (V2.0) data lane and 10Gbps across four lanes. Pixel or AXI interfaces can be used as the host interface and are compatible with both continuous and non-continuous clock modes.

MIPI CSI-2 Controller IP core both Tx and Rx supports RAW-16 and RAW-20 colour depths and has the potential to increase virtual channels from 4 to 32 while decreasing Latency Reduction and Transport Efficiency (LRTE), high-performance applications, and high-resolution imaging. It can send photos and videos in 1080p, 4K, and 8K resolutions. It is appropriate for single and multi-camera implementations. Differential Pulse Code Modulation (DPCM) compression reduces bandwidth while delivering SNR images devoid of compression artifacts for vision applications.

MIPI DSI Controller IP core which is compliant with DSI-2 v1.1 and optimized for high performance, low power, and small footprint. The cores are fully featured, enabling both host (Tx) and peripheral (Rx) communication, as well as several user interface options, and are extremely programmable. There are 64 and 32-bit core widths available, allowing the user to trade off clock rate vs size.

In addition to MIPI C-D Combo Tx/Rx PHY IP with MIPI CSI/DSI Controller Silicon IP core, T2M‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, DDR, MIPI (CSI, DSI, Soundwire, I3C), 10/100/1000 Ethernet, programmable SerDes, SD/eMMCs, Analog IPs and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge process nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand-alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology expert, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

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