Meeting the Major Challenges of Modern Memory Design

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www.synopsys.com, Jun. 15, 2023 – 

Overview

Memory lies at the heart of every electronics application, and demand is growing all the time. Users want ever greater capacity, throughput, and reliability. At the same time, time to market (TTM) goals and competitive pressures mandate that memories be developed in ever shorter project schedules. These requirements put enormous pressure on designers of discrete memory chips, memory dies in 2.5D/3D configurations, and memories embedded within system-on-chip (SoC) devices.

Among the many challenges of memory design, three stand out: scaling performance and capacity; ensuring silicon safety and reliability; and reducing development turnaround time (TAT). This white paper discusses these challenges, describes the requirements for viable solutions, and introduces the Synopsys approach to addressing the challenges. It presents four major areas of innovation in memory development: design technology co-optimization, memory design shift left, digitization of memory design, and design for reliability.

Scaling Challenges

Unlike in the past, the design and development of new memories is not independent of process development. With today's deep submicron technologies, much closer cooperation between the design and process teams is necessary to provide the required improvements in memory density and performance. There are several factors and trends driving this evolution:

• The slowing of Moore's Law means that memory designers can no longer count on regular, predictable benefits from scaling alone
• The end of Dennard scaling has led to early design/architectural optimization, detailed optimization of physical layout design rules, and new process recipes
• The slowing of supply voltage scaling and the increasing effect of leakage currents have limited reductions in device power at new nodes
• Bitline and wordline parasitics have an increased effect in DRAM arrays
• The need for sufficiently high storage capacitor values drives higher aspect ratio capacitor structures and the use of materials with higher dielectric constants
• DRAM scaling has become more challenging due to cell capacitance, cell contact resistance, and row hammer effects
• Scaling of DRAM and NAND periphery is increasingly impacted by process variability, which reduces the design margin for the sensing circuits
• The number of layers in 3D NAND devices has grown to around 200 and is projected to
• increase to more than 500, driving innovation in high aspect ratio etching processes and process techniques to improve channel conductivity

All these effects have produced a technology-design gap that has resulted in suboptimal devices and process recipes, suboptimal memory performance, and late-stage design changes that increase TTM. Minimizing this gap requires co-optimization of materials, processes, and device structures with target designs to ensure directional correctness, and this need will grow even stronger with emerging memory technologies.

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