RISC-V Summit Europe 2023 ended in Barcelona but the #riscv revolution has only just begun

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As more RISC-V silicon would flood the market in coming decades, functional correctness of silicon and time-to-market will play a crucial role. #formalverification would play a critical role in determining if we can ship silicon without respins affected by logic bugs in an efficient manner

fr.linkedin.com/?trk=guest_homepage-basic_nav-header-logo, Jun. 10, 2023 – 

Formal is great for bug hunting but it is the only way to establish exhaustive proofs that bugs don't exist. We have brought over three decades of research & industry experience in practical formal verification to our formalISA app which has not only found tons of bugs in numerous processors but continues to be used for exhaustive proofs for 32-bit and 64-bit cores.

We have automated debug by building a bespoke debugger in the form of i-RADAR and we can provide assurances that our methods are sound by giving you a six-dimensional coverage model via scenario coverage. Your teams can see the extensive reporting and coverage information via our SURF tool embedded in formalISA.

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