imec looks to process flow for sub-nm stacked CFET transistors

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imec in Belgium is developing a process flow for next generation CFET transistors with backside connections to complete the nanosheet family in the logic technology roadmap

https://www.eenewseurope.com/, Jul. 05, 2023 – 

A roadmap for transistor architectures

"Today, the semiconductor industry is in a transition period from FinFET to Nanosheet, a device architecture that will extend the roadmap with multiple logic technology generations," said Hans Mertens, principal member of technical staff at imec.

"Along the road, we might introduce the forksheet, an advanced nanosheet architecture that we proposed a few years ago, with reduced separation between adjacent devices, offering both scaling and performance advantages compared to conventional nanosheet," he said.

"Towards the end of the decade, we expect the complementary FET (CFET) to enter the roadmap. In this device architecture, n- and pMOS devices are stacked on top of each other, removing for the first time the n-p separation from standard cell height considerations. When complemented with advanced technologies to contact the transistors, CFET will allow to gradually push track heights from 5T to 4T and even beyond, effectively shrinking standard cell size substantially."

From processing point of view, CFET fabrication is challenging due to the nMOS-pMOS vertically stacked structure, and Mertens say imec is in the early stages of pathfinding. Several types of CFET have been proposed, with different construction techniques. In a sequential process flow, top-tier devices are processed sequentially after transfer of a blanket semiconductor layer by wafer bonding on top of bottom-tier devices. Monolithic integration involves building the vertical device architecture on a single substrate.

Monolithic CFET

imec is focussing on developing a monolithic CFET process as this offer the fastest path to CFET introduction for chip makers.

"Within our logic program, imec and its partners focus on monolithic CFET integration, as this integration scheme is the least disruptive compared to existing nanosheet-type process flows," said Anne Vandooren, principal member of technical staff at imec.

"Nevertheless, the vertical stacking of layers from which both devices will be fabricated drives a need for high-aspect ratio patterning, selective deposition and removal of materials, and the deposition of high-quality (epi-)films. In addition, some CFET-specific process modules will need to be introduced to enable vertical isolation in the gate and contact part of the cross-section.

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