The European Project Creating Extensible, Energy-Efficient RISC-V CPUs

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Some European researchers are developing open-source RISC-V cores to compete with x86 and Arm, and are relying on only €8 million in funding.

www.hpcwire.com/, Jun. 28, 2023 – 

Details about the ambitious eProcessor project were shared at the International Supercomputing Conference (ISC) in Hamburg, Germany, last month. The conference is a showcase for pan-European high-performance computing projects.

The project's goal is to develop building blocks – including single-core and multi-core RISC-V cores – for European organizations building basic computing devices or high-performance systems. The researchers are developing other modules, such as AI cores, that can be tacked on to RISC-V CPUs.

The researchers are topping off the chip designs with a complete open-source software stack, including the OS. System builders will get a full stack of offerings to build RISC-V systems while keeping the cost minimal.

Many researchers are building RISC-V cores, but the eProcessor is ambitious in scope. It is operating on funding of €8 million, with €4 million from the EU. It is similar to work being done by fabless chip designers developing both the hardware and software, but it doesn't use cutting-edge memory and throughput technologies.

"This project is an ambitious combination of processor design, based on the RISC-V open-source hardware ISA, applications, and system software extending pre-existing intellectual property, combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains," the researchers wrote in a poster presented at ISC.

One of the project's goals is to "advance the state-of-the-art for the ML accelerators by developing arithmetic units to support simultaneously a wide range of reduced and mixed precision (1, 2, 4, 8-bit) as well as explore new formats (8- and 16-bit bfloat) for reduced precision floating-point for ML training."

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