Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC's N3E Process

Find the Latest SoC Solutions
for... Automotive... IoT... Security... Audio... Video

Although the path from chip design to tape-out was never an easy one to navigate, this journey has become ever more challenging due to a growing demand for lower-power, higher-bandwidth applications. Indeed, chip architectures continue to increase in complexity on the most advanced FinFET nodes as billions of transistors are packed into smaller, denser silicon packages to meet new power, performance, and area (PPA) requirements. That's why Synopsys and TSMC continuously collaborate to deliver the chip design industry's broadest silicon-proven IP portfolio on the latest process technologies.

www.design-reuse-embedded.com/, Jul. 19, 2023 – 

Synopsys' IP silicon success for the TSMC N3E node–which provides a fast path to TSMC N3P, N3AE, and beyond–minimizes integration risks and accelerates time to market. Read on to learn how Synopsys IP enables semiconductor companies to develop advanced SoCs and multi-die systems for a wide range applications and technologies including artificial intelligence (AI) and machine learning (ML), high-performance computing (HPC), and mobile.

Leveraging the Semiconductor Industry's Broadest TSMC N3E IP Portfolio

The explosion of data that defines the zettabyte age requires sophisticated semiconductor IP capable of handling the lowest latency operations and fastest transfers within a power-efficient envelope. From purpose-built AI accelerators and advanced driver assistance systems (ADAS) to hyperscale data centers and high-resolution displays, Synopsys Interface and Foundation IP on TSMC's N3E process is helping chip and system designers streamline integration and reduce development cycles.

Adopted by leading semiconductor companies, Synopsys IP on TSMC's 3nm process can be paired with TSMC-certified digital and custom design flows based on the latest design rule manual (DRM) and process design kits (PDKs). Synopsys' expansive silicon IP portfolio for TSMC's N3E process comprises:

• Interface IP: 112G Ethernet LR-MAX, Ethernet (1G-10G), LPDDR5X, DDR5, PCIe 4.0/5.0/6.0, USB 3.2/DisplayPort 1.4, eUSB2, UCIe PHY, MIPI C/D-PHY, and MIPI M-PHY IP.
• Foundation IP: Embedded memories, logic libraries and I/O solutions.

click here to read more...

 Back