Efabless Design Challenge Winners Advance the Power of AI in Chip Design

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PALO ALTO, Calif., Sept. 13, 2023 (GLOBE NEWSWIRE) -- Efabless Corporation, the creator platform for chips, today announced the first, second, and third-place winners of its Second AI Generated Open-Source Silicon Design Challenge. The challenge was open to a broad range of participants including IC designers, university students, professors, industry experts, and even those who had never designed a chip before.

www.efabless.com/, Sept. 13, 2023 – 

The AI Generated Open-Source Silicon Design Challenges are a part of Efabless' initiative to democratize the use of Generative AI for chip design. The initiative drives innovation and learning in the chip design community by:

• Advancing the capabilities of generative AI use for chip design and verification, as well as secure device implementation.
• Enabling and engaging a global community of adopters and innovators by sharing their learnings and best practices in open public forums.
• Accelerating the creation of open-source data sets with designs that are broadly and openly accessible.

In the Challenges, participants create digital designs in Verilog using generative AI tools such as ChatGPT and Bard. The Verilog designs are then implemented using the chipIgnite Caravel SoC template and an open-source design flow such as OpenLane. Participants submit all prompts used to generate a complete RTL model for the design along with verification testbenches that demonstrate the design meets the intended functionality.

The first-place winner of the contest is AI by AI by Emilio Isaac Baungarten Leon. The design is a dedicated hardware Integrated Circuit (IC) for a Convolutional Neural Network (CNN) that classifies the MNIST dataset written with the help of ChatGPT and documents the entire design process from the Python environment of TensorFlow to Verilog. This approach demonstrates the incredible possibilities of AI-driven design.

The second-place winner of the contest is MASC-AI-Synthesized-Cryptoprocessor by Mark Zakharov. This design is a RISC-V Crypto extension leveraging the capabilities of GPT-4. The unique aspect of this project is the use of DSLX as the hardware description language, verification with co-simulation code generated by GPT-4, and additional automatically generated verification tests.

The third-place winner of the contest is Caravel-Vector-Coprocessor-AI by William Salcedo. The design adds basic vector instructions to the Caravel Management SoC. All code, besides file paths, was written using ChatGPT. This includes test cases, C libraries, blocks, etc. In this project, GPT-4 served as a pair programmer which followed the instructions of a human that was aware of how the microarchitecture would look.

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