Accelerating RISC-V development with network-on-chip IP

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The development of RISC-V-based SoCs can be accelerated by leveraging the plug-and-play capabilities offered by NoC technologies.

www.ednasia.com/, Sept. 27, 2023 – 

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

A recent trend is the widespread adoption of RISC-V cores, which are built upon open standard RISC-V instruction set architecture (ISA). This system is available through royalty-free open-source licenses.

Here, the utilization of network-on-chip (NoC) technologies' plug-and-play capabilities has emerged as an effective strategy to accelerate the integration of RISC-V-based systems. This approach facilitates seamless connections between processor cores or clusters and intellectual property (IP) blocks from multiple vendors.

Network-on-chip basics

Using a NoC interconnect IP offers several advantages. The NoC can extend across the whole device, with each IP having one or more interfaces that span the entire SoC. These interfaces have their own data widths, operate at varying clock frequencies, and utilize diverse protocols such as OCP, APB, AHB, AXI, STBus, and DTL commonly adopted by SoC designers. Each of these interfaces links to a corresponding network interface unit (NIU), also referred to as a socket.

The NIU's role is to receive data from a transmitting IP and then organize and serialize this data into a standardized format suitable for network transmission. Multiple packets can be in transit simultaneously. Upon arrival at its destination, the associated socket performs the reverse action by deserializing and undoing the packetization before presenting the data to the relevant IP. This process is done in accordance with the protocol and interface specifications linked to that particular IP.

A straightforward illustration of IP blocks could be visualized as solid logic blocks. Additionally, an SoC usually utilizes a single NoC. Figure 1 illustrates a basic NoC configuration.

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