RISC-V Releases Abound Ahead of 2023 RISC-V Summit

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At the 2023 North America RISC-V Summit, dozens of presenters will showcase RISC-V innovations in desktop computing and wearable applications.

www.allaboutcircuits.com/, Oct. 28, 2023 – 

With industry interest in RISC-V exploding–even forming the core of China's national plan to cut reliance on Western IP–a full ecosystem has arisen around the open-source ISA. Many of these innovations are slated for presentation at the 2023 RISC-V summit in Santa Clara, California. According to the event's official website, the summit will include keynotes, breakout sessions, and an expo hall supported by key sponsors like Andes Technology, OpenHW Group, and Google.

Ahead of the conference, several big players in RISC-V development have come forward with new releases and collaborations.

Andes Unveils RISC-V Cores for IoT

Andes Technology, a diamond sponsor of the event, is a leading provider of RISC-V IP for SoCs. Recently, the company announced two new RISC-V cores: D23 and N225. Andes says the cores are designed to be as power-efficient yet performant as possible.

Both cores share some critical features but differ in others. For starters, both the D23 and N225 use a 3-stage pipeline, single-issue architecture. Single issue indicates that a single instruction is issued to the pipeline per clock cycle; the Clocks Per Instruction (CPI) is 1. Additionally, both cores are performant, with the D23 featuring 4.55 Coremark/MHz and the N225 achieving 4.4 Coremark/MHz.

Ahead of the conference, several big players in RISC-V development have come forward with new releases and collaborations.

Andes Unveils RISC-V Cores for IoT

Andes Technology, a diamond sponsor of the event, is a leading provider of RISC-V IP for SoCs. Recently, the company announced two new RISC-V cores: D23 and N225. Andes says the cores are designed to be as power-efficient yet performant as possible.

Both cores share some critical features but differ in others. For starters, both the D23 and N225 use a 3-stage pipeline, single-issue architecture. Single issue indicates that a single instruction is issued to the pipeline per clock cycle; the Clocks Per Instruction (CPI) is 1. Additionally, both cores are performant, with the D23 featuring 4.55 Coremark/MHz and the N225 achieving 4.4 Coremark/MHz.

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