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CXL Consortium Announces Compute Express Link 3.1 Specification Release

Nov. 14, 2023 – 

BEAVERTON, Ore.-- November 14, 2023 --The CXL Consortium, an industry standards body developing and promoting an open coherent interconnect, today announced the release of the Compute Express Link™ (CXL™) 3.1 specification with improved fabric manageability to take CXL beyond the rack and enable disaggregated systems. The CXL 3.1 Specification builds on previous iterations to optimize resource utilization, create trusted compute environments as needed, extend memory sharing and pooling to avoid stranded memory, and facilitate memory sharing between accelerators.

“The CXL 3.1 specification incorporates new features requested by the CXL community to create disaggregated systems and keep up with high-performance computational workloads,” said Larrie Carr, CXL Consortium President. “With the support of our members, we continue to develop and promote CXL technology to enable an interoperable ecosystem of heterogeneous memory and computing solutions.”

Highlights of the CXL 3.1 specification feature

CXL Consortium members to demo live technology solutions at SC’23

CXL IP Cores

The Consortium will host demos at the CXL pavilion (Booth #1301) at Supercomputing 2023, November 14-17 at the Colorado Convention Center in Denver. Additionally, CXL Consortium representatives will participate in the following sessions:


About the CXL™ Consortium

The CXL Consortium is an industry standards body dedicated to advancing Compute Express Link™ (CXL™) – an open coherent interconnect technology. A high-speed interconnect offering coherency and memory semantics, CXL uses high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. For more information or to join, visit www.computeexpresslink.org.


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