- ARC-V Processor IP
- ARC-V RHX-105 dual-issue, 32-bit multi-core RISC-V processor for real-time applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- E2 Series - Power & area optimized: 2-3-stage, single-issue pipeline, as small as 13.5k gates
- E3 Series - High performance 32-bit RISC-V Processor
- E7 Series - Ultra High Performance 32-bit RISC-V Embedded Processor
- More Products...
IP-SOC DAYS 2025 IP-SOC DAYS 2024 IP-SOC DAYS 2023 IP-SOC DAYS 2022 IP-SOC DAYS 2021 IP-SOC 2024 IP-SOC 2023 IP-SOC 2022 IP-SOC 2021
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Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition
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New RISC-V Core Extends Renesas' Industry-Leading Embedded Processing Portfolio
www.renesas.com/us/en, Nov. 30, 2023 –
TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm® Cortex®-M architecture.
RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.