- ARC-V Processor IP
- ARC-V RHX-105 dual-issue, 32-bit multi-core RISC-V processor for real-time applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- E2 Series - Power & area optimized: 2-3-stage, single-issue pipeline, as small as 13.5k gates
- E3 Series - High performance 32-bit RISC-V Processor
- E7 Series - Ultra High Performance 32-bit RISC-V Embedded Processor
- More Products...
|
IP-SOC DAYS 2025 IP-SOC DAYS 2024 IP-SOC DAYS 2023 IP-SOC DAYS 2022 IP-SOC DAYS 2021 IP-SOC 2024 IP-SOC 2023 IP-SOC 2022 IP-SOC 2021
|
|||||||
|
|
||||||
Renesas Champions the RISC-V Cause With Its Own 32-bit RISC-V CPU
- Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design (May. 16, 2025)
- Semidynamics: From RISC-V with AI to AI with RISC-V (May. 16, 2025)
- TSMC Board of Directors Meeting Resolutions (May. 16, 2025)
- Arm Evolves Compute Platform Naming for the AI Era (May. 16, 2025)
- Secafy Licenses Menta's eFPGA IP to Power Chiplet-Based Secure Semiconductor Designs (May. 15, 2025)
- See Latest News>>
Renesas has announced one of the first independently developed 32-bit RISC-V CPUs.
www.allaboutcircuits.com/, Dec. 06, 2023 –
Renesas, long a major player in the industrial MCU and CPU universe, has announced the release of a new CPU family with a RISC-V core of its own design. The design joins Renesas' 32-bit arsenal, which includes Arm Cortex-M-based CPUs and the proprietary RX family. The devices are targeted at the general-purpose RISC-V market for consumer, industrial, healthcare, and IoT applications.
This is not the first RISC-V-based product from Renesas, but its prior offerings used designs by third-party IP providers, such as Andes Technology. With this new offering, Renesas designed and built its own from the open-source specifications. Having its own design RISC-V instruction set architecture (ISA) will enable greater customization for products in its core markets and allow Renesas to have control over product release timelines. Ultimately, RISC-V was created to give companies this type of flexibility without the extra work and limitations that come with a fully proprietary ISA.
A Win-Win for Renesas and RISC-V
RISC-V (pronounced "risk five") is an open-source instruction set architecture, originally designed as part of a 2010 research project out of the Parallel Computing Laboratory at the University of California, Berkeley. In recent years, RISC-V has gained broad acceptance and is now available as an IP package from multiple IP vendors and as hard and soft processor cores in FPGAs.
RISC-V has been gaining wider acceptance, and a full portfolio of offerings from Renesas is a significant win for the architecture. Renesas has a large footprint in automotive, industrial, and IoT solutions. Its processor portfolio contains custom architectures, Arm-based products, and now, RISC-V CPUs. Renesas may not be the most well-known microcontroller brand, but it is one of the most widely used due to its extensive automotive and industrial control products. A general-purpose RISC-V core from Renesas may help the company grow into more diverse markets by producing a powerful component based on the up-and-coming architecture.
Back
Contact Us
Partnership Offers