World's first UCIe heterogeneous chiplet test chip

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Synopsys and Intel have developed the first test chip with the Universal Chiplet Interconnect Express (UCIe) protocol used to connect chiplets made on different processes.

www.eenewseurope.com, Dec. 18, 2023 – 

The test chip demonstrated UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, simulating each test chip using the Synopsys VCS functional verification tool.

Intel's test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology and was paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.

The combination of devices built on different process technologies is key for boosting the complexity of system in a single package using the UCIe protocol.

The collaboration uncovered some lessons learned that they plan to share with the UCIe Consortium says Manuel Mota, senior staff product manager for high-speed interface IP for the Synopsys Solutions Group.

As silicon manufacturing takes a long time, and validating that everything works as intended is also cost- and time-intensive, finding a way to use existing test chips or silicon can be a good way to assess compatibility.

Designing multi-die systems involves extensive planning, especially if for re-use of the package or board designs. Building in as much flexibility as possible in the boards is one way to provide options for future use.

An open standard like UCIe provides confidence of interoperability. When one company controls both sides of a link, there are, of course, no concerns about whether each side will work together. But moving forward, over the next few years, he expects to see more companies who prefer not to build both sides, instead choosing to buy components off the market which could well be made on different technologies. This was highlighted at the recent DVcon Europe panel on chiplets.

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