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China Is All In on a RISC-V Future
The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "Examining China's Grand Strategy For RISC-V" is part of their China Brief segment and leans on the security concerns of RISC-V.
www.hpcwire.com/, Jan. 08, 2024 –
It is an open processor instruction set architecture (ISA) for those unfamiliar with RISC-V. Unlike ISAs from Intel or Arm, the RISC-V ISA is an open standard that allows underlying software to communicate in a consistent fashion with the processor that adheres to the ISA. Intel and ARM ISAs must be licensed for a fee from their respective owners (AMD has an x86 license from Intel). RISC-V was developed around 2010 at the University of California, Berkeley, and was conceived as an alternative to the complexities and costs of proprietary ISAs.
To support open cooperation and growth the RISC-V Foundation was established in 2015 with the following founding members Andes, Antmicro, Bluespec, CEVA, Codasip, Cortus, Esperanto, Espressif, ETH Zurich, Google, IBM, ICT, IIT Madras, Lattice, lowRISC, Microchip, MIT (Csail), Qualcomm, Rambus, Rumble, SiFive, Syntacore and Technolution. Since its founding, many Chinese companies have joined the foundation, including the Chinese Academy of Sciences (CAS), listed as a Development Partner.
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