Satisfy Your Chiplet Craving at the Chiplet Summit

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This must-attend event in Santa Clara will delve into all aspects of chiplet technology.

www.designnews.com/, Jan. 31, 2024 – 

At a Glance

• The all-important issues of establishing chiplet infrastructure will be covered in keynotes and tech sessions.
• Other sessions will cover design, testing, applications, and state-of-the-art chiplet R&D.

The information-rich content lineup at the Chiplet Summit February 6-8 includes several keynote discussions that will explore industry efforts to create a chiplet design and manufacturing infrastructure, a key hurdle in adopting the technology.

For instance, Brian Rea of the UCIe Consortium, an industry consortium promoting the UCIe (Universal Chiplet Interconnect Express) technology, will talk about enabling an open chiplet ecosystem at the package level. The UCIe standard is one of two chiplet interfaces, the other being the Bunch-of-Wires (BoW) from the Open Compute Platform Foundation.

Also touting an open chiplet model are Bapi Vinnakota and Cliff Grossner from the Open Compute Project. The speakers will talk about projects to standardize design models, establish third-party testing, define best practices for assembly, and create a standard high-performance, low-power die-to-die interface.

Francisco Socal and Mark Knight, both from Arm, will talk about the concept of reusable chiplets for heterogenous computing. The speakers expect new standards will help designers build reusable chipsets to integrate into multiple systems. The standards will extend the Advanced Microcontroller Bus Architecture (AMBA)'s on-chip Coherent Bus Interface (CHI) to a chip-to-chip (C2C) version suitable for connecting chip(let)-to-chip(let).

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